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0:25
Hello and welcome to the next edition of NPTEL online course on Microelectronics, devices to circuits. We will start today’s module on last signal operation of operational amplifiers and second order effects. The reason for doing this module was that typically as of now we are assuming that the input to the signal or input signal to the operational amplifier’s peak to peak values are relatively small and therefore even when you multiplied that with the open loop gain
0:54
of the operational amplifier, it never crosses the values of plus Vcc and minus Vee. Remember in my previous discussion which we had during the starting of the module on Operational amplifiers, you will understand or you will notice that whenever you are dealing with Op Amps, your op amps are primarily having a negative and a positive terminal and you also had plus Vcc and minus Vcc or minus Vee and you had one output terminal here.
1:30
Now if you multiply typically A, say suppose this is equals to plus 15 and this is equals to minus 15 and if the difference between the two signals is say 1 milli amp, 1 milli volt let us suppose and A is equals to 100 or maybe even 10 to the power 3, so I get output Vout to be equals to 10 to the power 3 into 1 milli volt. So that becomes equals to 1 volt, now 1 volt is much smaller as compared to Vcc, right. Similarly, if this now comes out to be 10 milli volt then I get 10 volt as the output,
2:09
so if this is, so Vin is 1 milli volt, I get Vout to be equals to 1 volt. If Vin equals to 10 milli volt, I get Vout to be equals to 10 volt and so on and so forth. Now therefore if this Vin is let us suppose say 20 then my Vout should be equal to 20 volts but that exceeds this value here and here which means that my output waveform which I will get will be much larger than plus 15 which is being said by the power supply.
2:46
So I am basically allowing the device to trip and therefore there will be the output waveform will be clipped at plus 15. Now what we will be studying in this module is that thing only that given a possibility that you do not, you let the whole system to saturate and you allow the voltage to go beyond the permissible values then how does the operational amplifier behaves. So that will be the major goal of this study.
3:17
Before that let me give you a small problem and you might try to solve it, the methodology I can give it to you. Say I have an input, this is regarding an integrator right. So I have an integrator in which the input waveform, this is t is equals to 0 and this is t equals to 1 millisecond and this is equals to 1 volt. So in an integrator I am giving a square wave, just like as input waveform whose peak value is 1 volt and whose width, pulse width is 1 millisecond and you need to calculate how
3:50
it looks like, so how it looks like we need to calculate. Let me draw for you, so before that if the resistance is given to be as 10K and C is given to be as 10 nano farads. So I get V0(t), right is equal to 1 by CR integral 0 to t 1 dt where t is between 1 millisecond and 0. So if I solve it I get V0(t) to e equals to minus 10 t by putting the values of C and R. So if you look very carefully this is basically a negative sign with a 10, so it will be a
4:29
ramp so and the voltage goes like this, this will be typically a ramp here, ramp till how much, minus 10 volts and after this it will be a straight line once again right, there will be 0, sorry it will go to, it will go to 0 here. Why it will go to 0 here because see here you are integrating, you are integrating it right? You are integrating it, so when the, so this is what you get as far as integration is concerned.
4:53
This is how it looks like right, so integration of a constant value will give you a constant output and that is the reason we will get it, whereas if you look at the differentiator for example, differentiator is basically dVin/dt into RC, well that is how you look into the differentiator which means that in a differentiator if you get a constant. For example, the same profile if I ever got, this is the input then the rising edge right,
5:26
rising edge my dV/dt would have been very large, so I would have got a spike here, but when my voltage goes to constant, then constant differential is always 0 and therefore this will, I will just see a spike here and then I will since it is coming down I will see a spike here. So a differentiator looks something like this and integrator looks something like this. So this is a pretty wonderful method, differentiators are pretty wonderful methods for generating
5:57
spikes out of given waveforms but differentiators are very seldom used because they influence large amount, they insert large amount of noise because of electromagnetic interference and so on and so forth whereas integrators do not do that. So just for information’s sake this is in consonance or in continuation of my earlier discussion as far as this course was, as far as this course was concerned. Let me come to therefore the next part here and let me come to the large signal operation
6:23
and let us go step by step what we will be doing here. So we will be looking into large signal operation of op-amp, we understand what is a slew rate, why is it important as far as designing is concerned, in operational amplifier design is concerned. We will also look into one important point that we are assuming till now that your loop, your gain is infinitely large and your bandwidths are also large but in reality your bandwidths
6:49
are always restricted bandwidths right, and gains are also restricted. And therefore under such a scenario how will your open loop gain change and how will your input impedance and your output impedance change. We will also look into Frequency Response, Gain Bandwidth Product, the concept of Offset Voltage and the concept of Offset Compensation Voltage and then a Bias Current, right. We will take one of them individually and understand, try to understand the basic features
7:16
of these individual voltages or understand the basic concept, right. You see we had just now discussed that an operational amplifier if you give an input voltage, my output voltage will be as I discussed with you, difference of the two voltage multiplied by a which means that if the difference remains the same right, that my output voltage will be independent on the both the voltages. I hope you understand this point, because A into V2 minus V1.
7:47
As long as V2 minus V1 is held constant and I do not mind and my V0 is constant, output voltage is constant. This is basically sort of a linear property of the device which primarily means that in such a scenario your amplification is independent of the input voltages but then operational amplifiers remain linear for a limited range of output voltages right and what happens is that as you reach towards plus Vcc and minus Vcc in the output side, you try to drive
8:20
or or the signal tries to drive the operational amplifier into saturation, right. As it enters into saturation, there is a problem and the problem is non-linearity comes into picture to a larger extent. Now another limitation of the operation of operational amplifier is that the output current is limited by the maximum specified value which means what, an operational amplifier remember, output current is given by even if you take an integrator or a differentiator.
8:50
So if you see it will be resistance here and the capacitance here right, or maybe the inverting one will be much easier to understand so I have got R2 and R1 here, as I discussed with you suppose this is Vin then Vin by R is the current flowing through this resistor but since this is a virtual ground I would expect to see all the current to move to this R and therefore R2 will also have the same current here, the same current will reach at the output of the current.
9:16
But please understand the total output current is limited by power dissipation of operational amplifier right, so operational amplifiers are designed to operate at optimal power dissipations. Now if the current is very high right, it might trouble the operation of an operational amplifier and therefore you always have a limit on the total amount of current flowing through the operational amplifier in the output loop factor. So this is one problem area which people face.
9:46
The third problem area is of the slew-rate, you would not be as far as designing is considered in most of the cases if it is a small signal you would not be having these problems coming in the picture but whenever you have a large-signal model for operational amplifier you might have these problems. Slew-rate is primarily if you look very closely, look at the second point will give you a give you an idea.
10:13
If a large sinusoidal signal or a step function is applied to an operational amplifier circuit the input stage can be overdriven and the small-signal model will no longer apply, as I was saying to you. Now if there is a heavy non-linear distortion when there is a large distortion signal, then we define it to be the slew-rate limited signal. So how do you define slew-rate, the maximum rate of change at the output.
10:41
The maximum rate of change possible at the output of a real op-amp is known as the slew-rate which means that let me just show you then we will come back here. This is my definition dV0/dt means the rate of change of output voltage with respect to time, the maximum it can sustain and why I am saying the maximum it can sustain is there is certain specific reasons for that. The maximum, the reason for that is that the variation of the voltage with respect to time
11:12
may may, let it be at input or output is always governed by the RC time constant of that particular point or that particular node, so you cannot expect that if I give an input which is suddenly rising like a step voltage, you would not expect that the same performance will be at the output of your operational amplifier, it will be always delayed and there will be always a RC time constant available to you at the output side right, so we define slew-rate
11:40
as the maximum rate of change of output voltage with respect to time which the operational amplifier can safely sustain. You make it slightly larger than that output variation and you would not get any change in the output cycle right or it would not be or will be actually slew-rate limited output supply. So as I was discussing with you let us suppose I have a voltage follower right, I discussed this point or I discussed this circuit in your previous turn as well and let us suppose
12:05
I have a voltage follower. In this voltage follower I give a step input which is given as VI, what I am seeing is that because of the step input ideally I would have seen the output to follow the input because it is given to the positive terminal, non-inverting terminal and therefore output should ideally follow like this but because op-amp has got a problem, therefore output will always be a like this which means that it will flow or it will rise at the maximum pace.
12:38
So if the slew-rates are large it will be like this, if the slew-rates are small, it will be something like this, you got my point. Therefore, these are known as slew-rate limited operational amplifiers right. So they will tell you that it is basically 20 milli volts per second or per microsecond which means that for every one microsecond change in the output I would expect to see a 20 milli volt change in the output voltage that is the maximum that the op-amp can sustain.
13:11
Anything larger than that it cannot be sustained with operational amplifiers, right? So this is the basic concept here which you see. Now as I discussed with you, therefore, if you look at the curve which is the last one here then this slope which you see that means it will be slew-rate limited then this slope gives you the value which is the ωT into, ωT is the unity gain bandwidth frequency multiplied by voltage must be less than equals to slew-rate.
13:39
So so this we will discuss later on if time permits. But ωT into, ωT into V is the input voltage given is basically the rate of change of my output voltage and that should be always less than the slew-rate, then you will get such type curve in reality, right. So I get V0 by Vt, V0 is the output voltage by Vt which is the input voltage is 1 by 1 plus s by ωT where ωT is basically the 3 db bandwidth frequency, so if you do transform,
14:10
Laplace transform of this one you get V0, inverse Laplace transform sorry, you get V0(t) equals to V0 into 1 minus e to the power minus ωT. So 1 minus e to the power minus ωT into t into V0 is equals to V0, so you see as the time increases this quantity will drop down this quantity will increase and that is what is happening, fine. So this is Slew-rate dependent phenomena which you see. Now if you, what we were discussing in the previous turn was that if you have an inverting
14:40
amplifier, I mean inverting amplifier, then the output will be 180 degree phase shifted with respect to input and therefore you put a negative sign in your closed loop gain. So I get ACL equals to minus R2 by R1, remember? Now what has happened is that my loop gain or my gain was considered to be very high right and therefore my, but if it is not high and it is restricted by a certain value, for example AOL which is the open loop gain, then the closed loop gain is related to the open
15:10
loop gain by this this factor, right? And this is what I get; this is what I get as the difference in the open loop gain and the closed loop gain. So just to show you this basic concept as far as effect of finite loop gain is considered. Let me just show it you what I am talking about and let me show you how it works out that, let us suppose I have a filter whose output characteristics look something like this so I have, this is basically your, this is your 3 dB bandwidth or 3 dB point and the
15:49
voltage is defined as fb let us suppose where it cuts is defined as fT unity gain because it is 0 dB, this is my gain V0 by Vi in dB and this is my ω in terms of frequency we will get some value. Now so what I am trying to tell you is that open loop gain, open loop gain, let us suppose it drops down or it falls then how does it influence my in this thing. So I have a low pass filter let us suppose and transfer function is given by A(S) equals
16:24
to A0 upon 1 plus s by ωb, where ωb is basically my this frequency here. So in terms of jω I get, I just replace S by jω I get A0 upon 1 plus jω by ωb, right? So, so what I am trying to tell you is that let us suppose now you assume that your frequency is increased by 10 times as compared to ωb, so I am somewhere here right, then I get A of jω equals to A0 into ωb by ω, got the point, jω, why because if ω is very very
17:04
large as compared to ωb this quantity will be very large as compared to 1 and I get A0 into ωb by ω s equals to A of jω right? So if I take the mod value of a of jω then I get this to be equals to A0 ωb by ω. So I get the gain to be equals to A0 multiplied by ωb by ω. A0 is fixed because that is open loop gain multiplied by ωb by ω. This is my sort of a closed loop gain and a finite loop gain which you see, right.
17:37
So this gives you a value, now at ω equals to ωT where you have got a unity gain bandwidth product I will automatically have this equals to 1 and therefore a of jω will be approximately given as ωT by jω because this is 1 ωb will convert to ωT and ωT by jω I get where fT will be given as ωT by 2π, right? So this is your unity gain unity gain bandwidth frequency right? And therefore if you want to find out this, if you want to find out the this the magnitude
18:22
of A of jω from this case right, I get this to be equals to ωT by ω, this is nothing but fT by f. So it is the ratio of the unity gain frequency divided by the frequency at which you are trying to find out the gain, the ratio of that will be equals to your gain right at that particular frequency. Now that is with the consideration that your finite loop gain is already available to you. Now generally if this is a single pole dominated transfer function, single, if there is a single
18:57
pole on the left half plain, then you will automatically this will be around minus 20 dB per decade or minus 6 dB per octave. So please try to find out why it is 6 dB per octave, I leave it as an exercise to you but you can ask questions later on through the discussion forum but try to find out why it can be also referred to as minus 6 dB per octave or minus 20 dB per decade provided you have a single pole on the S plain.
19:29
So if you have a single pole here then we define that to be as a this thing, if there are multiple poles, for example this complex conjugate poles here so there are two poles, so it will be 20 times n dB per decade. I will not derive it here, so this is minus 20 times n dB. So you multiply 20 with the number of poles, so if there are two poles, 40 dB per decade. So you would expect to see a steeper fall. So larger the number of poles right, more steeper will be your fall in the low-pass
20:05
filter and better will be your characteristics, you will be reaching to the much. So the ideal characteristic is something like this right, for a low pass filter. So now you will get much more better because this fall will be very fast here, so which means higher number of poles means higher order of your filter, you automatically get a larger and larger value of your input profile and that is what is known as a dominant pole approximation. This is known as a dominant dominant pole, right?
20:35
So this is as far as understanding the dominant pole approximation is concerned. Now if I take a closed loop control or a closed loop consideration I get R2 by R1 into 1 plus 1 by AOL 1 plus R2 by R1. I am not deriving it in the class but this is what you get out of it. Now you see if your open loop gain AOL is extremely high or infinitely high then this quantity, this quantity goes to 0 and I get again R2 by R1 which is basically my initial
21:03
inverting mode, remember, inverting mode operational amplifier. Got the point? So when your open loop gain is very very high 10 to the power 7 in the ideal cases, you get a closed loop gain almost near to R2 by R1 but if your AOL is not very high it is 10 or 20 or 30 or 40 whatever, then these also lower your overall closed loop gain right and that is the inverting amplifier case. Let us look at the non-inverting amplifier case, exactly the same only thing the numerator
21:31
is replaced by 1 plus R2 by R1 and you have denominator given as this similarly if AOL goes to a very high value, this quantity this quantity goes to 0 and therefore I get 1 plus R2 by R1 as the value of your ACL closed loop gain, right? And as you can see that for the small signal model this has been replaced by a voltage source of a value AOL into V2 minus V1, fine. And this is the current source so I am assuming that so I will be assuming that I1 equals
22:00
to I2, well assuming or it is true in a sense true also because this is basically high impedance node available here, right? So I have a finite open-loop gain that gives me a non-inverting amplifier here. Now if I want to find out the inverting amplifier closed loop input resistance then I have to find out Rif which is I1 by V1. Now if you look at this this thing here, so I have got R1, R2 and let us suppose I have a load resistance RL.
22:29
This can be made to equivalent small-signal models, so this is my input impedance Ri, this is my R2 which is the feedback resistance here and I have got output resistance R 0 and minus AOL into V1 because you are inserting your signal into the inverting terminal and therefore minus AOL into V1, why V1, because V2 is grounded. So I get minus AOL into V1 into RL is the external node. If you solve it by doing simple simple derivations I get this the overall picture as the input
22:58
resistances, so sorry so I get this plus sorry this will be equal to, so this will be here equal to right and I get, 1 over that will give you the value of your Rif input impedance for the closed loop gain. If I do a non-inverting exactly the same happens, non-inverting case Rif case comes out to be equal to this one right and this is sorry this is actually VI by II, right, input current and this is the input resistance 1 plus AOL plus R2.
23:32
So as you can see if this goes to very high value right, your Rif also goes to a very high value right and this is true also if a open loop gain is very very high of an operational amplifier your input impedances will also be very high right and you can get this value here. So is it a R1, R2, RL is exactly the same as the pervious case and we get this into consideration here with Vd is the voltage difference between R1 and R2 between this point and this point, right.
24:00
We come to the non-zero output resistance; typically the ideal op-amp has a zero output resistance. We have already seen that but and the output voltage therefore is independent of the resistances seen at the output load and that is therefore op-amp starts to act like an ideal, what is an ideal voltage source? Ideal voltage source is a source which gives you, wherein you can draw any large current but the voltage across the that source will always remain constant right and that was
24:26
the ideal voltage source which means that there is no loading, in reality not true that the output the ideal op-amps will have some non zero in resistance in the output side. As I discussed with you therefore the actual op-amp circuit will have a non-zero output resistance which means that that output voltage and therefore the closed loop gain is as function of the load impedance, right. Why? Because see if let us suppose, let us suppose that output voltage is independent of load
24:56
impedances right, so whatever your load impedance is 10 kilo ohm, 5 kilo ohm, 100 ohm or 40 ohm or shortage, the voltage level at the particular point will remain fixed and so when your impedance levels are say 100 kilo ohm, you will be drawing a smaller current but if voltage remains fixed right. So when you want to make your voltage independent of load impedances then you assume that op-amp is behaving like an ideal voltage source, in reality not true as I discussed with you
25:25
and therefore your output voltage will start to become a function of your output impedance, right? And therefore when you output impedance changes, your voltage will also change. It is given by this formula here1 by Rof to be equals to 1 by Ro, Ro is the, 1 by Ro is basically my output impedance under ideal conditions right, but with this you get AOL coming into picture. So if you just make it, if you just do the reciprocal of this one I get Rof to be equals
25:53
to Ro right and then you reciprocate this 1 plus R2 by R1 right, divide it by AOL. As you can see make open-loop gain infinitely large and Rof goes to 0. So ideal output output voltage always be close to 0. Look at the frequency response, as I discussed with you frequency response for any other cases will be just like a low-pass filter and AOL, open loop gain is given as Ao upon 1 plus j by fPD, PD is basically your 3 dB point, so fT which is the unity gain frequency
26:27
is given by fPD into Ao and therefore the closed loop gain is given by AOL upon 1 plus β times AOL, right? And therefore you get f 3dB equals to f Pd into AOL upon ACLO, which means that 3 dB frequency depends upon your fPD and also depends upon the ratio of your open loop gain on the closed loop gain, right. So if you know, if this quantity is high which generally it is then your 3dB bandwidth is higher than fPD, right?
26:55
And that is what you get here fPD is basically my 3dB, 3dB bandwidth and f PD is my, fPD is this point where it starts to go down and this f3dB is the bandwidth at which you have a 3dB gain here. So we will again come back to this frequency response later, all in a detailed manner. At this stage you can understand it is almost behave like an integrator and low-pass integrator. Now gain bandwidth product is given by closed loop gain if you look very carefully, unity
27:29
fT, fT is unity gain bandwidth is given by CLO which means that the closed loop circuitry 1 plus f unity; f unity is fT divided by f PD, f PD is basically my 3dB into AOL by ACLO. And therefore I get f T equals to, so f unity is equals to f T, provided I get A0 by ACLO very high, right. So what happens is that when you open-loop your gain is higher, when your closed loop your gain falls down but your 3dB bandwidth increases so your initial 3dB was this much
28:01
right and now your 3dB has improved by this much, so your 3dB bandwidth is an and that is the reason your GBP, Gain Bandwidth Product is always constant. So the first case without when you are in an open loop conditions, you automatically have your gain very very high, in the closed loop conditions your gains falls off drastically, right. Okay We come to another important issue of an operational amplifier and that is known as an Offset Voltage.
28:27
Now ideally if you remember if I short the input of my operational amplifier, the inverting and the non-inverting input, then for this, then I will get 0 output available to me because V2 minus V1 is 0. In reality not true, there is some amount of DC voltage available to me in the output side. So I can see here the output DC offset voltage is measured open-loop output voltage when the input voltage is zero, right.
28:53
The input DC offset voltage is defined as the input differential voltage that must be applied to the open-loop op-amp to produce a zero output voltage. You got the point? So you see when you do not apply anything you get some voltage right? Now if we apply a voltage in the reverse direction, then this high value will go down to zero. So this amount of voltage is, input side voltage is defined as my input differential offset voltage right or input offset voltage.
29:24
I can have an output offset voltage also I can have an input offset voltage. What is an input offset voltage, at the input side the amount of voltage you need to give differential between two voltage sources so that the output goes to zero is my defined as my input differential voltage. I will not go into the details of the derivations here but typically if you look very carefully assuming that, I have a differential pair here right and it is driven by this, by this ideal current source here.
29:56
And so this is the VGS1 is the drive voltage, VGS2 and I am trying to do the voltage difference between V0 and V1. So offset voltage will be given as VGS1 minus VGS2 right, remember because these are the two inputs I am giving to the operational amplifier. Now I am assuming that these voltages are not equal, so I am trying to find out the difference between the two voltages, right. So in reality if you look very carefully, in the previous slide if you, if you go back
30:23
to the previous slide see this is the VOS I am giving here and I have grounded this I am giving VOS, so that this goes to 0. So with this concept I have applied VOS as VGS1 minus VGS2 right. This is from assuming that there is saturation I get root of ID1 upon Kn1 where Kn1 is µn1 Cox (W/L) by l plus VTN1 threshold voltage of N-MOS minus this whole quantity where ID1 is given by this ID2 is given by this. ID1 is the current flowing through this arm and ID2 is the current flowing through these
30:57
two arm. If you put all these values back into this equation, do a small solution assuming that VTN1 equals to VTN2, so they cancel out. I get this output voltage the value here, right, where, just let me see, yes. So I will get this output voltage where IQ is the sum of the two currents which you see and delta Kn is basically the difference in the value of your, these two values, right. Difference of these two values and Kn is basically the one of the, Kn is the process transconductance
31:29
parameter of the differential pair. As you can see here higher the current more will be offset in a negative sense right, because it is the inverting terminal which I am giving to you. Okay. We come to the offset compensation voltage compensation, so there are two methods by which you can compensate the offset voltages and these two compensations are externally compensation, externally connected of set compensation network and with the null offset terminals.
31:58
So we would not go into the details but I will give you an idea how it works out in a very simple manner. So you see I have Vi here which I am giving. I also have a 100 ohm R1 and 100 kilo ohm here. I have a potential divider at R3, so If I move this up or down right, some amount of resistance will be in series 200 kilo ohm and that will be in parallel to 100 ohm here and this will be feeding the voltage to R1, you getting my point?
32:25
So by simply choosing the potential divider network up or down I can actually make the resistance value in a potential divider network change right and make it exactly equal to the offset voltage. So what I do, what I initially experimentally how how I do it, I go on shifting this potential divider network up or down and check out that when V0 equals to 0. So when V0 is equals to 0, I stop and that is basically my input offset voltage, right.
32:55
So this is one of the methodologies people adopt across the current. Then you also have an Input Bias Current, well this is very simple. They will be generally symmetrical if everything is matched for the top and bottom. If the input stage is symmetrical with all the corresponding elements match, IB1 will has to be equal to IB2. So I define IB equals to IB1 plus IB2 the average current and offset current is defined as difference between IB1 and IB2.
33:21
In reality, IB1 and IB2 must be equal but they are not and therefore there will be difference. Okay. I come to Bias Current Compensation, so I was doing voltage compensation there. Now I do a bias compensation and this bias compensation is given by this manner by that which we have got VX and VY here and simply by choosing appropriate value of R3, I can choose IB1 equal to IB2, right. I will not go into further details of this one, because this is slightly higher than
33:51
what you are supposed to know at this stage and therefore you need not worry about from where I am getting this bias compensation. So let me recapitulate what we did, we were actually looking into an op-amp slewing action. What is the meaning of slew right and what is slew rate, slew rate limited operation? What is a DC offset voltage right and how do you define DC offset voltages? What is the meaning of saturation, operational amplifier saturation?
34:21
What is the meaning of input offset voltage VOS? And how can we determine the input offset voltage, similarly what is the input offset current and how can you remove it. So this we have learned in this module and this takes care of approximately our whole understanding of the analog part of the syllabus. So from next turn onwards, we will start with the combinational logic which is a digital part right? And for the next ten five to six hours of our lecture which is left we will be actually
34:49
doing a lot of differential a lot of digital logic design. So this is where we stop our mixed signal or analog block out of the circuits, so if you look at the whole structure of the course it is first devices which is the first few weeks, one or two weeks. Then subsequently from three to lecture week number seven it is primarily a analog flow and then we have a digital flow at the last places. So next time onwards we will start the digital flow. Thank you very much.
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